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HDD32M64F8K
DDR SDRAM Module 256Mbyte (32Mx64bit), based on16Mx8,4Banks, 4K Ref., SMM, Part No. HDD32M64F8K
GENERAL DESCRIPTION
The HDD32M64F8K is a 32M x 64 bit Double Data Rate(DDR) Synchronous Dynamic RAM high-density memory module. The module consists of sixteen CMOS 16M x 8 bit with 4banks DDR SDRAMs in 66pin TSOP-II 400mil packages and 2K EEPROM in 8-pin TSSOP package on a 200-pin glass-epoxy. Four 0.1uF decoupling capacitors are mounted on the printed circuit board in parallel for each DDR SDRAM. The HSD32M64F8K is a SMM(Stackable Memory Module type) .Synchronous design allows precise cycle control with the use of system clock. Data I/O transactions are possible on both edges of DQS. Range of operating frequencies, programmable latencies and burst lengths allows the same device to be useful for a variety of high bandwidth, high performance memory system applications. All module components may be powered from a single 2.5V DC power supply and all inputs and outputs are SSTL_2 compatible.
FEATURES
* Part Identification
HDD32M64F8K - 10A : HDD32M64F8K - 13A : HDD32M64F8K - 13B : 100MHz (CL=2) 133MHz (CL=2) 133MHz (CL=2.5)
* 256MB(32Mx64) Unbuffered DDR SMM based on 16Mx8 DDR SDRSM * 2.5V 0.2V VDD and VDDQ power supply * Auto & self refresh capability (4096 Cycles/64ms) * All input and output are compatible with SSTL_2 interface * Data(DQ), Data strobes and write masks latched on the rising and falling edges of the clock * All Addresses and control inputs except Data(DQ), Data strobes and Data masks latched on the rising edges of the clock * MRS cycle with address key programs - Latency (Access from column address) : 2, 2.5 - Burst length : 2, 4, 8 - Data scramble : Sequential & Interleave * Data(DQ), Data strobes and write masks latched on the rising and falling edges of the clock * All Addresses and control inputs except Data(DQ), Data strobes and Data masks latched on the rising edges of the clock * The used device is 4M x 8bit x 4Banks DDR SDRAM
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PIN ASSIGNMENT
P1 PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 Symbol /CS0 /CS1 VSS CKE0 CKE1 NC VDD CK0 CK1 NC VSS NC DM0 DM4 VDDQ NC NC VSS NC DQS0 DQS4 VDD NC DQ0 DQ1 VSS DQ2 DQ3 VDDQ DQ4 DQ5 DQ6 VSS DQ7 PIN 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 Symbol DQ15 DQ14 VDDQ DQ13 DQ12 DQ11 VSS DQ10 DQ9 DQ8 VDD *SA0 *SA1 VSS *SA2 VDDQ VDD /RAS VSS /CAS /CK0 /CK1 VDD /CK2 CK2 /WE VSS NC DM1 DM5 VDDQ NC VREF VSS PIN 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 Symbol NC DQS1 DQS5 VDD NC DQ39 DQ38 VSS DQ37 DQ36 VDDQ DQ35 DQ34 DQ33 VSS DQ32 DQ40 DQ41 VDDQ DQ42 DQ43 DQ44 VSS DQ45 DQ46 DQ47 *SCL *WP *VSPD VSS *SDA VDDIN PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 Symbol VDDQ A3 VSS A2 A1 A0 VDD A10 A11 BA0 VSS BA1 DM2 DM6 VDDQ NC NC VSS DQS7 DQS2 NC VDD DQ31 DQ30 DQ29 VSS DQ28 DQ27 VDDQ DQ26 DQ25 DQ24 VSS DQ16 PIN 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 P2
HDD32M64F8K
Symbol DQ17 DQ18 VDDQ DQ19 DQ20 DQ21 VSS DQ22 DQ23 NC(CB6) VDD NC(CB4) NC(CB2) VSS NC(CB0) VDDQ VDD A4 VSS A5 A6 A7 VDD A8 A9 NC(A12) VSS DM3 DM7 NC(DM8) VDDQ NC NC(A13) VSS
PIN 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
Symbol NC(DQS8) DQS3 DQS6 VDD DQ56 DQ57 DQ58 VSS DQ59 DQ60 VDDQ DQ61 DQ62 DQ63 VSS DQ55 DQ54 DQ53 VDDQ DQ52 DQ51 DQ50 VSS DQ49 DQ48 NC(CB7) VDD NC(CB5) NC(CB3) VSS NC(CB1) VDD
* These pins should be NC in the system which does not support SPD
PIN
A0~A11 BA0~BA1 DQ0~DQ63 CB0~CB7 DQS0~DQS7 DM0~DM7 CK0~CK2,/CK0~/CK2 CKE0~CKE1 /CS0~/CS1 /RAS /CAS
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PIN DESCRIPTION
Address input Bank Select Address Data input/output Check bit(Data input/output) Data Strobe input/output Data-in Mask Clock input Clock enable input Chip Select input Row Address strobe Column Address strobe
2
PIN
VDD VDDQ VREF VSPD VSS SA0~SA2 SDA SCL WP VDDIN NC
PIN DESCRIPTION
Power supply(2.5V) Power supply for DQs(2.5V) Power supply for reference Serial EEPROM Power supply(3.3) Ground Address in EEPROM Serial data I/O Serial clock Write protection VDD indentification flag No connection
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FUNCTIONAL BLOCK DIAGRAM
HDD32M64F8K
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
U1
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
U10
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
U5
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
U15
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
U2
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
U11
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
U6
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
U16
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
U3
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
U13
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
U8
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
U18
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
U4
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
U14
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
U9
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
U19
Stacking
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PIN FUNCTION DESCRIPTION
Pin CK, /CK Clock Name
HDD32M64F8K
Input Function CK and CK are differential clock inputs. All address and control input signals are sam-pled on the positive edge of CK and negative edge of CK. Output (read) data is referenced to both edges of CK. Internal clock signals are derived from CK/CK. CKE HIGH activates, and CKE LOW deactivates internal clock signals, and device input buffers and output drivers. Deactivating the clock provides PRECHARGE POWER-DOWN and SELF REFRESH operation (all banks idle), or ACTIVE POWER-DOWN(row ACTIVE in any bank). CKE is synchronous for all functions except for disabling outputs, which is achieved asynchronously. Input buffers, excluding CK, CK and CKE are disabled during power-down and self refresh modes, providing low standby power. CKE will recognizean LVCMOS LOW level prior to VREF being stable on power-up. CS enables(registered LOW) and disables(registered HIGH) the command decoder. All commands are masked when CS is registered HIGH. CS provides for external bank selection on systems with multiple banks. CS is considered part of the command code. Row/column addresses are multiplexed on the same pins.
CKE
Clock Enable
/CS
Chip Select
A0 ~ A11
Address
Row address : RA0 ~ RA11, Column address : CA0 ~ CA9 BA0 and BA1 define to which bank an ACTIVE, READ, WRITE or PRE-CHARGE
BA0 ~ BA1
Bank select address
command is being applied. Latches row addresses on the positive going edge of the CLK with /RAS low.
/RAS
Row address strobe
Enables row access & precharge. Latches column addresses on the positive going edge of the CLK with /CAS low.
/CAS
Columnaddress strobe
Enables column access. Enables write operation and row precharge.
/WE
Write enable
Latches data in starting from /CAS, /WE active. Output with read data, input with write data. Edge-aligned with read data, cen-
DQS0 ~ 7
Data Strobe
tered in write data. Used to capture write data. DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH along with that input data during a WRITE access. DM is sampled
DM0~7
Input Data Mask
on both edges of DQS. DM pins include dummy loading internally, to matches the DQ and DQS load-ing.
DQ0 ~ 63
Data input/output
Data inputs/outputs are multiplexed on the same pins. WP pin is connected to Vcc.
WP
Write Protection
When WP is " high" EEPROM Programming will be inhibited and the entire , memory will be write-protected. DQ Power Supply : +2.5V 0.2V. Power Supply : +2.5V 0.2V (device specific). DQ Ground. SSTL_2 reference voltage.
VDDQ VDD VSS VREF
Supply Supply Supply Supply
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ABSOLUTE MAXIMUM RATINGS
PARAMETER Voltage on any pin relative to Vss Voltage on VDD supply relative to Vss Voltage on VDDQ supply relative to Vss Storage temperature Power dissipation SYMBOL VIN, VOUT VDD VDDQ TSTG PD RATING -o.5 ~ 3.6 -1.0 ~ 3.6 -0.5 ~ 3.6 -55 ~ +150 16.0
HDD32M64F8K
UNTE V V V C W mA
Short circuit current IOS 50 Notes: Operation at above absolute maximum rating can adversely affect device reliability
DC OPERATING CONDITIONS
(Recommended operating conditions (Voltage referenced to Vss = 0V, TA = 0 to 70 ) C)
PARAMETER Supply Voltage I/O Supply Voltage I/O Reference Voltage I/O Termination Voltage(system) Input High Voltage Input Low Voltage Input Voltage Level, CK and /CK inputs Input Differential Voltage, CK and /CK inputs Input leakage current Output leakage current Output High current (VOUT = 1.95V) SYMBOL VDD VDDQ VREF VTT VIH (DC) VIL (DC) VIN (DC) VID (DC) I LI I OZ I OH MIN 2.3 2.3 1.15 VREF - 0.04 VREF + 0.15 -0.3 -0.3 0.3 -2 -5 -16.8 MAX 2.7 2.7 1.35 VREF + 0.04 VREF + 0.3 VREF - 0.15 VDDQ + 0.3 VDDQ + 0.6 2 5 UNIT V V V V V V V V uA uA mA mA 3 1 2 NOTE
Output Low current (VOUT = 0.35V) I OL 16.8 Notes : 1.Typically, the value of VREF is expected to be about 0.5* VDD of the transmitting device. VREF is expected to track variation in VDDQ . 2.Peak to peak AC noise on VREF may not exceed 2% VREF (DC). 3.VTT of the transmitting device must track VREF of the receiving device.
CAPACITANCE
(VDD = min to max, VDDQ = 2.5V to 2.7V, TA = 25 f = 100MHz) C,
DESCRIPTION SYMBO L MIN MAX UNITS
Input capacitance(A0~A11, BA0~BA1, /RAS, /CAS,/WE) Input capacitance(CKE0,CKE1) Input capacitance(/CS0~/CS1) Input capacitance(CLK0, CLK1,CLK2) Input capacitance(DM0~DM7) Data input/output capacitance (DQ0 ~ DQ63, DQS0~DQS7)
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CIN1 CIN2 CIN3 CIN4 CIN5 COUT1
93 63 58 30 10 10
107 77 72 45 15 15
pF pF pF pF pF pF
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DC CHARACTERISTICS
(Recommended operating condition unless otherwise noted, VDD = 2.5V, T =25 C)
SYMBO PARAMETER L CONDITION Burst length = 2 Operating current IDD1 (One bank active) tRC tRC(min), CL=2.5 IOUT = 0mA, Active-Read-Presharge CKE VIL(max) IDD2P tCK = tCK(min), All banks idle CKE VIH(min) IDD2N /CSVIH(min), tCK = tCK(min) non power-down mode Active standby current in IDD3P power-down mode Active standby current in Active-Read-Presharge, non power-down mode (One bank active) tCK(min) Burst length = 2 Operating current (Read) IDD4R tRC = tRC(min), IOUT = 0mA, Burst length = 2 Operating current (Write) IDD4W tRC = tRC(min) CL=2 Auto refresh current Self refresh current IDD5 IDD6 tRC tREF(min) CKE 0.2V 2720 32 2880 32 5 1840 2240 CL=2. 5 CL=2 CL=2. 1840 2160 IDD3N tRC=tRAS(max), tCK = 720 800 VIL(max), tCK = tCK(min) Onel banks, All banks idle, CKE 480 560 288 320 48 56 1520 1600 -10A -13A TEST VERSION
HDD32M64F8K
UNIT -13B mA 1600
NOTE
Precharge standby current in power-down mode Precharge standby current in
mA 56
mA 320
mA 560 mA 800
2160
mA
2240
mA
2880 32
mA mA
AC OPERATING CONDITIONS
PARAMETER
Input High (Logic 1) Voltage, DQ, DQS and DM signals Input Low (Logic 0) Voltage, DQ, DQS and DM signals. Input Differential Voltage, CK and CK inputs Input Crossing Point Voltage, CK and CK inputs STMBOL VIH (AC) VIL (AC) VID (AC) VIX (AC) 0.7 0.5*VDDQ-0.2
MIN
VREF + 0.35
MAX
UNIT
NOTE
VREF - 0.35 VDDQ+0.6 0.5*VDDQ+0.2
V V V 1 2
Notes: 1. VID is the magnitude of the difference between the input level on CK and the input on CK.
2.
The value of VIX is expected to equal 0.5* VDDQ of the transmitting device and must track variations in the DC level of the same
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HDD32M64F8K
AC OPERATING TEST CONDITIONS
PARAMETER Input reference voltage for Clock Input signal maximum peak swing Input signal minimum slew rate Input Levels(VIH/VIL) Input timing measurement reference level Output timing measurement reference level Output load condition VALUE 0.5 * VDDQ 1.5 1.0 VREF+0.35/VREF VREF VTT See Load Circuit UNIT V V V V V V V NOTE
AC CHARACTERISTICS (These AC charicteristics were tested on the Component)
DDR200 SYMBO PARAMETER L Row cycle time Refresh row cycle time Row active time /RAS to /CAS delay Row precharge time Row active to Row active delay Write recovery time Last data in to Read command Col. address to Col. address delay Clock cycle time CL=2.0 tCK CL=2.5
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DDR266A -13A
DDR266B -13B MIN 65 75 MAX ns ns 120K ns ns ns ns tCK tCK tCK 12 12 ns ns 1 1,2 1,2 3 3 3 3 2 UNIT NOTE
-10A MIN 70 80 48 20 20 15 2 1 1 10 12 12 120K MAX
MIN 65 75 45 20 20 15 2 1 1 7.5 7.5
MAX
tRC tRFC tRAS tRCD tRP tRRD tWR tCDLR tCCD
120K
45 20 20 15 2 1 1
12 12
10 7.5
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Clock high level width Clock low level width DQS-out access time from CK/CK Output data access time from CK/CK Data strobe edge to ouput data edge Read Preamble Read Postamble Data out high impedence time from CKtHZQ /CK CK to valid DQS-in DQS-in setup time DQS-in hold time DQS-in falling edge to CK rising-setup tDSS time DQS-in falling edge to CK rising hold tDSH time DQS-in high level width DQS-in low level width DQS-in cycle time Address and Control Input setup time Address and Control Input hold time Mode register set cycle time DQ & DM setup time to DQS DQ & DM hold time to DQS DQ & DM input pulse width Power down exit time Exit self refresh to write command Exit self refresh to bank active tXSA command Exit self refresh to read command Refresh interval time Output DQS valid window DQS write postamble time Notes : 1. 2. 3. Maximum burst refresh of 8. tXSR TREF TQH TWPST 200 15.6 0.35 0.25 200 15.6 0.35 0.25 80 tDQSH tDQSL tDSC tIS tIH tMRD tDS tDH tDIPW tPDEX tXSW 0.35 0.35 0.9 1.1 1.1 16 0.6 0.6 2 10 116 1.1 0.35 0.35 0.9 0.9 0.9 15 0.5 0.5 1.75 10 95 75 1.1 0.2 0.2 0.2 0.2 tDQSS tWPRES tWPREH 0.75 0 0.25 1.25 0.75 0 0.25 1.25 -0.8 +0.8 -0.75 +0.75 tCH tCL tDQSCK tAC tDQSQ tRPRE tRPST 0.45 0.45 -0.8 -0.8 0.9 0.4 0.55 0.55 +0.8 +0.8 +0.6 1.1 0.6 0.45 0.45 -0.75 -0.75 0.9 0.4 0.55 0.55 +0.75 +0.75 +0.5 1.1 0.6
HDD32M64F8K
0.45 0.45 -0.75 -0.75 0.9 0.4 -0.75 0.75 0 0.25 0.2 0.55 0.55 +0.75 +0.75 +0.5 1.1 0.6 +0.75 1.25 tCK tCK ns ns ns tCK tCK ns tCK ns tCK tCK 3 2
0.2 0.35 0.35 0.9 0.9 0.9 15 0.5 0.5 1.75 10 1.1
tCK tCK tCK tCK ns ns ns ns ns ns ns ns
75 ns 200 15.6 0.35 0.25 Cycle us tCK tCK 4 1
tHZQ transitions occurs in the same assess time windows as valid data transitions. These parameters are not referenced to a specific voltage level, but specify when the device output is no longer driving. The specific requirement is that DQS be valid(High-Low) on or before this CK edge. The case shown(DQS going from High_Z to logic Low) applies when no writes were previously in progress on the bus. If a previous write was in progress, DQS could be High at this time, depending on tDQSS.
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4.
HDD32M64F8K
The maximum limit for this parameter is not a device limit. The device will operate with a great value for this parameter, but system performance (bus turnaround) will degrade accordingly.
SIMPLIFIED TRUTH TABLE
COMMAND Register Register Extended MRS Mode register set Auto refresh Refresh Self refres h Auto disable Auto eable Auto disable Auto enable H Bank selection All banks Entry Exit Entry Exit H H L H L H H X H L X X L H L H L L H L X H L H L H L X V X X H X V X X H X H X H H H X V X X H X V precharge precharge H X L H L L L L X V X X H X V X X X X X X X V X X X 8 V X L H X H X V H X X precharge Entry Exit CKE n-1 H H H L H CKE n X X H L H X /CS L L L L H L /R A S L L L H X L /C A S L L L H X H /WE L L H H X H DM X X X X X V BA 0,1 A10/ AP OP code OP code X X Row address L H X L H L H X V H L Column Address (A0 ~ A9) Column Address (A0 ~ A9) 4,6 7 5 4 4 4 A11 A9~A0 NOTE 1,2 1,2 3 3 3 3
Bank active & row addr. Read & column address Write & column address Burst Stop Precharg e precharge
Clock suspend or active power down
Precharge power down mode DM
No operation command
(V=Valid, X=Don't care, H=Logic high, L=Logic low) Notes : 1. OP Code : Operand code A0 ~ A11 & BA0 ~ BA1 : Program keys. (@ MRS) 2. MRS can be issued only at all banks precharge state. A new command can be issued after 2 CLK cycles of MRS. 3. Auto refresh functions are as same as CBR refresh of DRAM. The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at all banks precharge state. 4. BA0 ~ BA1 : Bank select addresses. If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected. If both BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank B is selected. If both BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank C is selected. If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected. If A10/AP is "High" at row precharge, BA0 and BA1 is ignored and all banks are selected.
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HDD32M64F8K
5. During burst read or write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst. New row active of the associated bank can be issued at tRP after the end of burst. 6. Burst stop command is valid at every burst length. 7. DM sampled at the rising and falling edges of the DQS and Data-in are masked at the both edges (Write DM latency is 0)
PACKAGING INFORMATION
Unit : mm
Front - Side
Rear-Side
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ORDERING INFORMATION
HDD32M64F8K
Part Number
Density
Org.
Package
Ref.
Vcc
MODE
MAX.frq
HDD32M64F8K-10A HDD32M64F8K-13A HDD32M64F8K-13B
256MByte 256MByte 256MByte
32M x 64 32M x 64 32M x 64
200PIN SMM 200PIN SMM 200PIN SMM
4K 4K 4K
2.5V 2.5V 2.5V
DDR DDR DDR
100MHz/CL2 133MHz/CL2 133MHz/CL2.5
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